1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly relates to a semiconductor device having a configuration in which main I/O lines and power-supply lines are laid out on the same wiring layer.
2. Description of Related Art
As a type of semiconductor devices, an SDRAM (Synchronous Dynamic Random Access Memory) has been widely known. The SDRAM is a synchronous memory device that operates in synchronisms with a clock signal supplied from a controller device to input and output data. The SDRAM can increase its data transfer rate by using a faster clock signal.
In principle, a memory core of the SDRAM operates with an analog operation. A very weak charge that is read from a memory cell is amplified by a sense amplifier and then transferred to a peripheral circuit area via an I/O line system that is hierarchically structured. Therefore, in order to increase the data transfer rate, it is necessary not only to simply increase frequency of the clock signal, but to transfer data read from the memory cell to the peripheral circuit area with a faster speed.
Such a hierarchically structured I/O line system generally includes a local I/O line for transferring read data in a memory area and a main I/O line for transferring read data from a memory area to a peripheral circuit area. In this system, there is a case where the wiring length of the main I/O line is very long, for example, several millimeters. The local I/O line is connected to the main I/O line via a sub-amplifier, and data on the local I/O line is amplified by the sub-amplifier and transferred to the main I/O line.
The SDRAM also includes other types of wirings such as a column selection line and a power-supply line. The column selection line is connected to a column decoder provided in a column decoder area. The column selection line is laid out while passing above a memory cell array area, and controls a number of column switches. When a column select signal on the column selection line is activated, a corresponding bit line is connected to the local I/O line via a column switch in the sense amplifier.
The wirings described above are broadly classified into two types, that is, there are wirings extending in an X direction and those extending in a Y direction, and it is difficult to arrange both types of wirings on the same plane. Therefore, the SDRAM has a multi-level wiring stricture including a plurality of wiring layers to realize an efficient wiring layout. Specifically, on an upper layer of a memory cell array area where a cell transistor and a cell capacitor are formed, first to third wiring layers are provided in this order from bottom to top. The local or main I/O line, the column selection line, various types of power-supply lines, and the like are provided as these wiring layers. Because the higher the layer, the lower the wiring resistance, power-supply lines and a main I/O line having a long wiring length are preferably laid out as a higher wiring layer. For example, the column selection line is provided as the first wiring layer, the local I/O line is provided as the second wiring layer, and the main I/O line and various power-supply lines are provided as the third wiring layer.
Japanese Patent Application Laid-open No. 2000-49305 discloses a configuration of routing a vertical input/output line (a main I/O line) on a memory cell array by using a wiring of a third metal wiring layer. Japanese Patent Application Laid-open No. H6-68667 discloses a configuration in which a part of a wiring in a sense amplifier is laid out on the same wiring layer as a Y-selection line (a column selection line).
When a plurality of memory cells are highly integrated, the wiring density of a local I/O line and that of a main I/O line increase. For example, when the unit of allocation of local I/O lines is changed from 3 mats to 1.5 mats, the number of the local I/O lines doubles, and the number of main I/O lines required for connection with these local I/O lines also doubles. If these main I/O lines of an increased number are laid out by a conventional method, a wiring space in memory mats is occupied in a greater degree by a wiring area for the main I/O lines, and consequently a power-supply line area is reduced.
It is preferable that the resistance of power-supply lines is as low as possible. To this end, it is necessary to use a low-resistance wiring material and to design a wiring width wider. However, if the power-supply line area is reduced, the wiring width becomes narrow and the power-supply resistance in a memory cell array increases. This causes problems such as reduction in an operation margin.